Method of manufacturing a memory device having improved erasing characteristics

ABSTRACT

In a method of manufacturing a memory device having improved erasing characteristics, the method includes sequentially forming a tunneling oxide layer, a charge storing layer, and a blocking oxide layer on a semiconductor substrate; annealing the semiconductor substrate including the tunneling oxide layer, the charge storing layer, and the blocking oxide layer under a gas atmosphere so that the blocking oxide layer has a negative fixed oxide charge; forming a gate electrode on the blocking oxide layer with the negative fixed oxide charge and etching the tunneling oxide layer, the charge storing layer, and the blocking oxide layer to form a gate structure; and forming a first doped region and a second doped region in the semiconductor substrate at sides of the gate structure by doping the semiconductor substrate with a dopant.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims priority to Korean Patent Application No.10-2005-0023294, filed on Mar. 21, 2005, in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein in itsentirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of manufacturing a memorydevice having improved erasing characteristics, and more particularly,to a method of manufacturing a memory device in which an atmospheric gasand an annealing temperature are controlled so that a blocking oxidelayer can maintain a negative voltage during a process for forming thememory device.

2. Description of the Related Art

The development of semiconductor memory devices has focused onincreasing storage capacity while, at the same time, increasingprogramming and erasing speeds. A typical semiconductor memory arraystructure includes a plurality of memory unit cells connected bycircuitry and can be classified as a non-volatile memory device in whichinformation is retained when the power removed or as a volatile memorydevice such as a dynamic random access memory (DRAM) in whichinformation is retained only while power is applied. The informationstorage capacity of the memory device is proportional to the integrationdensity of the memory device. A typical unit cell of a semiconductormemory device includes one transistor and one capacitor.

Recently, new types of semiconductor memory devices having new operationprinciples have been introduced. For example, semiconductor memorydevices having a giant magneto-resistance (GMR) structure or a tunnelingmagneto-resistance (TMR) structure formed on a transistor have beenintroduced to utilize magnetic resistance characteristics. Also, newstructures of non-volatile semiconductor memory devices, such as a phasechange random access memory (PRAM) that utilizes a phase change materialto provide a data storage function, and a SONOS device having atunneling oxide layer, a change storing layer, and a blocking oxidelayer, have been introduced.

FIG. 1 is a cross-sectional view of a typical conventional SONOS memorydevice. Referring to FIG. 1, a first doped region 11 a and a seconddoped region 11 b doped with a dopant are formed in a semiconductorsubstrate 10. A channel region is defined in the semiconductor substrate10 between the first and second doped regions 11 a and 11 b. A gatestructure is formed on the semiconductor substrate 10 contacting thefirst doped region 11 a and the second doped region 11 b. The gatestructure has a structure in which a tunneling oxide layer 12, a chargestoring layer 13, a blocking oxide layer 14, and a gate electrode layer15 formed of a conductive material are sequentially formed.

Here, the tunneling oxide layer 12 contacts the first doped region 11 aand the second doped region 11 b of the semiconductor substrate 10, andcharge flowing in the channel region is stored in a trap site of thecharge storing layer 13 after the electrons pass through the tunnelingoxide layer 12. That is, the information programming of the memorydevice having the above structure is performed when the electrons passthrough the tunneling oxide layer 12 under a voltage applied to thememory device and are trapped in the trap site of the charge storinglayer 13.

In the SONOS memory device, the device threshold voltage V_(th) variesdepending on whether the electrons are trapped in the charge storinglayer 13. The blocking oxide layer 14 on the charge storing layer 13blocks electrons from leaking into the gate electrode layer 14 while theelectrons are trapped in the trap site of the charge storing layer 13,and blocks charge of the gate electrode layer 14 from being injectedinto the charge storing layer 13.

The SONOS memory device requires a thin tunneling oxide layer 15 toincrease the programming and erasing speed. However, this in turnreduces the information retention characteristics of the device. Thatis, the retention characteristics and erasing characteristics are in amutual trade-off relationship in accordance with the thickness of thetunneling oxide layer 12. To improve the inverse proportionalrelationship between the retention characteristics and the erasingcharacteristics, control over the characteristics of the blocking oxidelayer 14 is needed.

However, to prevent the blocking oxide layer 14 from tunneling electronsfrom the gate electrode layer 15, a thick blocking oxide layer 14 isdesired. However, if the blocking oxide layer 14 is too thick, thencontrol of the characteristics of the channel region by the gateelectrode layer 15 is adversely affected.

SUMMARY OF THE INVENTION

The present invention provides a method of manufacturing a semiconductormemory device with an improved memory erasing speed while maintainingthe retention characteristics of a SONOS memory device or a floatinggate type memory device.

In one aspect, the present invention is directed to a method ofmanufacturing a memory device, comprising: sequentially forming atunneling oxide layer, a charge storing layer, and a blocking oxidelayer on a semiconductor substrate; annealing the semiconductorsubstrate including the tunneling oxide layer, the charge storing layer,and the blocking oxide layer under a gas atmosphere so that the blockingoxide layer has a negative fixed oxide charge; forming a gate electrodeon the blocking oxide layer with the negative fixed oxide charge andetching the tunneling oxide layer, the charge storing layer, and theblocking oxide layer to form a gate structure; and forming a first dopedregion and a second doped region in the semiconductor substrate at sidesof the gate structure by doping the semiconductor substrate with adopant.

In one embodiment, the gas atmosphere for annealing comprises an elementselected from the group consisting of N, O, F, Si, P, S, Cl, C, As, Se,Br, Te, I, and At.

In another embodiment, the gas atmosphere for annealing is one selectedfrom O₂, RuO, and NH₃.

In another embodiment, the annealing is performed at a temperature of650° C. or more.

In another embodiment, the annealing is performed at a temperature inthe range of 700 to 1000° C.

In another aspect, the present invention is directed to a method ofmanufacturing a memory device, comprising: sequentially forming atunneling oxide layer, a charge storing layer, a blocking oxide layer,and a gate electrode layer on a semiconductor substrate; etching thetunneling oxide layer, the charge storing layer, the blocking oxidelayer, and the gate electrode layer to form a gate structure; forming afirst doped region and a second doped region in the semiconductorsubstrate at sides of the gate structure by doping the semiconductorsubstrate with a dopant; and annealing the semiconductor substrate andthe gate structure under a gas atmosphere so that the blocking oxidelayer has a negative fixed oxide charge;

In one embodiment, the gas atmosphere for annealing comprises an elementselected from the group consisting of N, O, F, Si, P, S, Cl, C, As, Se,Br, Te, I, and At.

In another embodiment, the gas atmosphere for annealing is one selectedfrom O₂, RuO, and NH₃.

In another embodiment, the annealing is performed at a temperature of650° C. or more.

In another embodiment, the annealing is performed at a temperature inthe range of 700 to 1000° C.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent by describing in detail exemplary embodimentsthereof with reference to the attached drawings, in which:

FIG. 1 is a cross-sectional view of a conventional memory device;

FIG. 2A is a cross-sectional view illustrating the structure of a memorydevice according to an embodiment of the present invention;

FIG. 2B is a graph showing the relationship between an initial stageflat band voltage V_(FB) and a minimum flat band voltage V_(FB) wheninformation is erased from a memory device;

FIGS. 3A through 3C are cross-sectional views illustrating a method ofmanufacturing a memory device having improved erasing characteristicsaccording to an embodiment of the present invention;

FIG. 4 is a graph showing erasing and retention characteristics of amemory device according to an embodiment of the present invention; and

FIGS. 5A through 5C are graphs showing electrical characteristics of amemory device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

The present invention will now be described more fully with reference tothe accompanying drawings, in which exemplary embodiments of theinvention are shown. In the drawings, the thicknesses of layers andregions are exaggerated for clarity.

FIG. 2A is a cross-sectional view illustrating the structure of a memorydevice having improved erasing characteristics according to anembodiment of the present invention.

Referring to FIG. 2A, a semiconductor substrate 20 having a first dopedregion 21 a and a second doped region 21 b doped with a dopant isprovided. A gate structure is formed on the semiconductor substrate 20between the first and second doped regions 21 a and 21 b. The gatestructure includes a tunneling oxide layer 22, a charge storing layer 23that includes a trap site for trapping charges, a blocking oxide layer24, and a gate electrode layer 25, sequentially formed on thesemiconductor substrate 20.

The tunneling oxide layer 22 can be formed of an insulating material,such as SiO₂, used for forming a conventional memory device. The chargestoring layer 23 includes a trap site for trapping charge passed throughthe tunneling oxide layer 22 from a channel region of the semiconductorsubstrate 20, and is formed of a high-k material having a dielectricconstant greater than that of the tunneling oxide layer 22 and theblocking oxide layer 24.

The gate electrode layer 25 can be formed of any conductive materialused for forming a conventional semiconductor memory device. Theblocking oxide layer 24 can have a negative fixed oxide charge whichwill be described with reference to FIG. 2B.

FIG. 2B is a graph showing the relationship between an initial stageflat band voltage V_(FB) and a minimum flat band voltage V_(FB) wheninformation is erased from a memory device. In a charge trapping memorydevice, as the flat band voltage V_(FB) increases, the retentioncharacteristics are improved. To erase information from a memory device,a large negative voltage is applied to the gate electrode layer 25.During the information erasing process, the minimum flat band voltagemay have a large negative value. That is, the minimum flat band voltagemay have values in the upper left side in FIG. 2B. A voltage V_(g)applied to the gate electrode layer 25, a flat band voltage V_(FB), anda voltage V_(ox) actually applied to the blocking oxide layer 24 havethe following relationship.V _(g) =V _(FB) +V _(ox)  [Equation 1]

The flat band voltage is proportional to −Q_(f)/C_(ox). Here, Q_(f) is acharge value of the blocking oxide layer 24, and C_(ox) is thecapacitance of the oxide film. In the erasing process, a voltage appliedto the gate electrode layer 25 has a large negative value and a voltageactually applied to the blocking oxide layer 24 varies according to theflat band voltage V_(FB). As it is seen from equation 1, when the flatband voltage V_(FB) has a positive value, the voltage applied to theblocking oxide layer 24 has a large negative value.

Accordingly, to allow the flat band voltage to have a positive value,the blocking oxide layer 24 can have a negative fixed oxide charge.

When the blocking oxide layer 24 has a negative fixed oxide charge, theband gap energy of the blocking oxide layer 24 is increased. Theincreased band gap energy of the blocking oxide layer 24 prevents themigration of charge from the gate electrode layer 25 to the chargestoring layer 23 by tunneling through the blocking oxide layer 24, thatis, the back tunneling of charge. Back tunneling can occur during anerasing process. Therefore, the electrical characteristics of the memorydevice are greatly improved when the blocking oxide layer 24 has thenegative fixed oxide charge.

A method of manufacturing a memory device as depicted in FIG. 2A, havingimproved erasing characteristics, according to an embodiment of thepresent invention will now be described with reference to FIGS. 3Athrough 3C. In the present invention, to manufacture the memory device,PVD, CVD, chemical doping, coating, ion implanting, annealing and rapidtemperature annealing (RTA) processes can be used.

Referring to FIG. 3A, a semiconductor substrate 20 is prepared. Thesemiconductor substrate 20 can be formed of any material used formanufacturing a conventional semiconductor memory device, including Si.A tunneling oxide layer 22 is deposited on the semiconductor substrate20. The tunneling oxide layer 22 can be formed to a thickness ofapproximately 2 to 4 nm by depositing an insulating material such asSiO₂ using a conventional semiconductor manufacturing process. After thetunneling oxide layer 22 is formed, a charge storing layer 23 isdeposited on the tunneling oxide layer 22. The charge storing layer 23can be formed of a high-k material having a high dielectric constant.

Next, a blocking oxide layer 24 is deposited on the charge storing layer23. The blocking oxide layer 24 can be formed to a thickness of 3.5 to20 nm using a dielectric material, such as SiO₂ or Al₂O₃. When theblocking oxide layer 24 is deposited, a rapid thermal annealing (RTA)process is performed at a temperature of, 650° C. or more in a chamberfilled with an atmospheric gas that includes an element selected fromthe group consisting of N, O, F, Si, P, S, Cl, C, As, Se, Br, Te, I, andAt so that the blocking oxide layer 24 can have a negative fixed oxidecharge. More specifically, the RTA process may be performed at atemperature in the range of 700 to 1000° C.

In one embodiment, the atmospheric gas can be, for example, O₂ gas, NH₃gas, or RuO gas. The pressure of the atmospheric gas is not an importantfactor, and can be controlled as necessary. In this manner, oxygen ornitrogen allows the blocking oxide layer 24 to have a negative fixedoxide charge. However, when N₂ gas or N₂O gas is injected into thechamber, the negative fixed oxide charge of the blocking oxide layer 24is not readily attained. Therefore, when nitride must be included in theblocking oxide layer 24, the atmospheric gas is preferably NH₃ gas.

Next, a gate electrode layer 25 is formed on the blocking oxide layer24. The gate electrode layer 25 can be formed of a conductive materialused for manufacturing a conventional semiconductor memory device.

Referring to FIGS. 3B and 3C, upper surfaces of the semiconductorsubstrate 20 on sides of the gate structure are exposed by etching bothsides of the tunneling oxide layer 22, the charge storing layer 23, theblocking oxide layer 24, and the gate electrode layer 25. The exposedupper surfaces of the semiconductor substrate 20 are doped with adopant. As the result of doping, a first doped region 21 a and a seconddoped region 21 b are formed in the semiconductor substrate 20. Finally,the first doped region 21 a and the second doped region 21 b areactivated by annealing the resultant product.

In the method of manufacturing the memory device described withreference to FIGS. 3A through 3C above, the process for allowing theblocking oxide layer 24 to have the negative fixed oxide charge isperformed immediately after forming the blocking oxide layer 24 on thecharge storing layer 23; however, the present invention is not limitedthereto. That is, in another embodiment, the negative fixed oxide chargeof the blocking oxide layer 24 can be selectively attained bypenetrating oxide or nitride, or another element or gas that results inthe blocking oxide layer having a negative field oxide layer, throughlateral side portions of the blocking oxide layer 24 after the gate isetched and the first doped region 21 a and the second doped region 21 bare formed.

FIG. 4 is a graph showing charge values of a memory device according toannealing temperatures of a specimen manufactured by the processesdescribed with reference to FIGS. 3A through 3C. Here, the x axisrepresents an annealing temperature under an O₂ atmosphere, and the yaxis represents N_(f)(Q_(f)/Q) values.

Referring to FIG. 4, when the specimen is annealed at a temperature of650° C. or more, it is seen that the blocking oxide layer 24 readilyattains the desired negative fixed oxide charge.

FIGS. 5A through 5C are graphs showing electrical characteristics of amemory device having improved erasing characteristics according to anembodiment of the present invention.

Referring to FIG. 5A, if a bias voltage of 13 to 17 V is applied to thespecimen when information is programmed, the threshold voltage V_(th) atthe programming state increases to greater than 1 V. Accordingly, thespecimen can be used as a memory device.

Referring to FIG. 5B, if a memory device is used for 10 years at atemperature of 85° C. after the memory device is annealed for two hoursat a temperature of 250° C., the estimated threshold voltage V_(th)shows a very small change of about −0.3V or more.

FIG. 5C shows the results of measuring flat band voltages V_(FB) byperforming programming/erasing (P/E) cycles. Referring to FIG. 5C, theflat band voltages V_(FB) of programming and erasing are substantiallyunchanged after 10⁴ P/E cycles.

While this invention has been particularly shown and described withreferences to preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade herein without departing from the spirit and scope of the inventionas defined by the appended claims.

For example, the present invention can be applied to all charge trappingtype memory devices that include a SONOS memory device.

According to the present invention, the stability of erasingcharacteristics of a memory device can be enhanced by forming a blockingoxide layer of a charge trapping type semiconductor memory device tohave a negative fixed oxide charge.

Also, by forming the blocking oxide layer to have a negative fixed oxidecharge, the band gap energy of the blocking oxide layer can beincreased. The increase in the band gap energy of the blocking oxidelayer prevents back tunneling of charge from the gate electrode layer tothe blocking oxide layer.

1. A method of manufacturing a memory device, comprising: sequentiallyforming a tunneling oxide layer, a charge storing layer, and a blockingoxide layer on a semiconductor substrate; annealing the semiconductorsubstrate including the tunneling oxide layer, the charge storing layer,and the blocking oxide layer under a gas atmosphere and at a temperatureso that the blocking oxide layer has a negative fixed oxide charge;forming a gate electrode on the blocking oxide layer with the negativefixed oxide charge and etching the tunneling oxide layer, the chargestoring layer, and the blocking oxide layer to form a gate structure;and forming a first doped region and a second doped region in thesemiconductor substrate at sides of the gate structure by doping thesemiconductor substrate with a dopant.
 2. The method of claim 1, whereinthe gas atmosphere for annealing comprises an element selected from thegroup consisting of N, O, F, Si, P, S, Cl, C, As, Sc, Br, Te, I, and At.3. The method of claim 1, wherein the gas atmosphere for annealing isone selected from O₂, RuO, and NH₃.
 4. The method of claim 1, whereinthe annealing is performed at a temperature of 650° C. or more.
 5. Themethod of claim 4, wherein the annealing is performed at a temperaturein the range of 700 to 1000° C.
 6. A method of manufacturing a memorydevice, comprising: sequentially forming a tunneling oxide layer, acharge storing layer, a blocking oxide layer, and a gate electrode layeron a semiconductor substrate; etching the tunneling oxide layer, thecharge storing layer, the blocking oxide layer, and the gate electrodelayer to form a gate structure; forming a first doped region and asecond doped region in the semiconductor substrate at sides of the gatestructure by doping the semiconductor substrate with a dopant; andannealing the semiconductor substrate and the gate structure under a gasatmosphere and at a temperature so that the blocking oxide layer has anegative fixed oxide charge.
 7. The method of claim 6, wherein the gasatmosphere for annealing comprises an element selected from the groupconsisting of N, O, F, Si, P, S, Cl, C, As, Se, Br, Te, I, and At. 8.The method of claim 6, wherein the gas atmosphere for annealing is oneselected from O₂, RuO, and NH₃.
 9. The method of claim 6, wherein theannealing is performed at a temperature of 650° C. or more.
 10. Themethod of claim 9, wherein the annealing is performed at a temperaturein the range of 700 to 1000° C.